Conventional phase locked loops (PLLs) are widely used in frequency synthesis, clock and data recovery, and other communications circuits. Conventional PLLs need to vary the loop bandwidth within the PLL. For example, an input clock is often noisy. If a clean clock is needed at the output of the PLL, a narrow bandwidth filter can be implemented to filter out the input noise. A different situation arises when the lock time is important. In such cases, a wide bandwidth PLL is needed to achieve fast locking. In some systems, a PLL is needed to switch between a narrow bandwidth mode and a wide bandwidth mode.
Referring to FIG. 1, a diagram of a system 10 is shown illustrating a conventional PLL. The system includes a charge pump 12, a phase frequency detector 14 and a loop filter 16. The charge pump 12 receives signals from the phase frequency detector 14. The loop filter 16 is shown implemented as a second order loop filter that converts the charge pump current ICP into a control voltage. The loop bandwidth of the PLL may be approximated by the following equation:
                              ϖ          u                =                              ICP            ⁢                                                  ⁢                          R              z                        ⁢                          K              vco                                            2            ⁢                                                  ⁢            π            ⁢                                                  ⁢            N                                              EQ        .                                  ⁢                  (          1          )                    where ICP is the charge pump current, Rz is the loop filter resistor, KVCO is the VCO gain, and N is the feedback frequency divider ratio. A stabilizing zero is formed by the resistor Rz and the capacitor Cz, with the frequency defined as ωz=1/(RZCZ). The loop filter 16 has two poles, a first pole at w=0 and a second pole at ωp=1/(RzC1).
To maintain stability, the loop may be designed to have a damping factor close to 1. The damping factor is given by the following equation:
                    ξ        =                                                            ICP                ⁢                                                                  ⁢                                  K                  vco                                                            2                ⁢                                                                  ⁢                π                ⁢                                                                  ⁢                                  N                  ⁡                                      (                                                                  C                        1                                            +                                              C                        z                                                              )                                                                                ⁢                      (                                          1                2                            ⁢                              R                z                            ⁢                              C                z                                      )                                              EQ        .                                  ⁢                  (          2          )                    The second pole ωp is chosen 3-10 times higher than ωu. In a scheme aimed at varying the loop bandwidth ωu, a guarantee that stability is not sacrificed is important.
It would be desirable to implement a variable loop bandwidth phase locked loop circuit that may accommodate a variety of applications.